Let's solve the problem step by step. --- ## **Given Function** \[ f = \overline{a + b \cdot c} \] --- ## **a) Write the equation for the nMOS network** **nMOS network implements \( f' \) (i.e., \( a + b \cdot c \)):** \[ f' = a + (b \cdot c) \] - **OR** (\(+\)): Parallel - **AND** (\(\cdot\)): Series So, in the nMOS pull-down network: - One branch is just \( a \) (nMOS transistor controlled by \( a \)), connected **in parallel** with - A **series** connection of \( b \) and \( c \) (nMOS transistors controlled by \( b \) and \( c \)). --- ## **b) Write the equation for the pMOS network** **pMOS network implements \( f \):** \[ f = \overline{a + b \cdot c} \] Apply DeMorgan's Law: \[ f = \overline{a + b \cdot c} = \overline{a} \cdot \overline{b \cdot c} = \overline{a} \cdot (\overline{b} + \overline{c}) \] - **AND** (\(\cdot\)): Series - **OR** (\(+\)): Parallel So, in the pMOS pull-up network: - One branch is \( \overline{a} \) (pMOS controlled by \( a \)), connected **in series** with - A **parallel** connection of \( \overline{b} \) and \( \overline{c} \) (pMOS transistors controlled by \( b \) and \( c \)), both inverted. --- ## **c) Construct a schematic for \( f \)** ### **nMOS Network (Pull-down to GND)** - **Parallel**: nMOS controlled by \( a \) - **Series**: nMOS controlled by \( b \) and \( c \) in series So, source to drain connections: - Output node is connected to GND if either \( a \) is ON (conducting), **or** both \( b \) and \( c \) are ON (conducting in series). ### **pMOS Network (Pull-up to Vdd)** - **Series**: pMOS controlled by \( a \) - **Parallel**: pMOS controlled by \( b \) and \( c \) (in parallel), both in series with the first So, source to drain connections: - Vdd is connected to output if \( a \) is OFF **and** either \( b \) is OFF **or** \( c \) is OFF. #### **Schematic Diagram Structure** ``` Vdd | | pMOS (a) (series) | +-----+------+ | | pMOS(b) pMOS(c) (parallel) | | +-----+------+ | Output | +-----+------+ | | nMOS(a) nMOS(b) | nMOS(c) | | GND GND ``` - The nMOS(b) and nMOS(c) are in series, and that series is in parallel to nMOS(a). --- ## **d) Verify the nMOS and pMOS networks are complements** - **nMOS**: Parallel \( a \) with series \( b \) - \( c \) - **pMOS**: Series \( a \) with parallel \( b \), \( c \) This matches the complementarity rule: **series in nMOS = parallel in pMOS** and vice versa. --- ## **Final Answer (Summary)** ### a) **nMOS equation:** \[ f' = a + (b \cdot c) \] ### b) **pMOS equation:** \[ f = \overline{a} \cdot (\overline{b} + \overline{c}) \] ### c) **CMOS schematic:** - **Pull-down (nMOS):** \( a \) in parallel with \( b \) series \( c \) - **Pull-up (pMOS):** \( a \) in series with parallel of \( b \) and \( c \) ### d) **Complementarity:** - nMOS and pMOS networks are proper complements. --- **Let me know if you want a drawn schematic!**