Let's break the problem into **2 steps** with explanations, and provide the final answer at the end: --- ### **Step 1: Expression Analysis and CMOS Logic Design** Given function: \[ f = x_1 (x_2 x_3 + x_4) \] First, rewrite it to see how the logic gates are arranged: - This is an AND between \( x_1 \) and an OR gate output (\( x_2 x_3 + x_4 \)), where \( x_2 x_3 \) is an AND. So, the gate level breakdown: - **First**, AND \( x_2 \) and \( x_3 \). - **Second**, OR the result with \( x_4 \). - **Third**, AND that result with \( x_1 \). Now, for CMOS implementation: - CMOS circuits are usually implemented using **NAND** and **NOR** gates, as they are more efficient. So, let's write the function in terms of NAND/NOR using De Morgan's Law. Let's find the **complement** first (\(\bar{f}\)), as CMOS logic is often designed for the pull-down network (NMOS) for \( f' \): \[ f = x_1 (x_2 x_3 + x_4) \] So, \[ \bar{f} = \overline{x_1 (x_2 x_3 + x_4)} = \bar{x}_1 + \overline{(x_2 x_3 + x_4)} \] \[ = \bar{x}_1 + (\bar{x}_2 + \bar{x}_3) \bar{x}_4 \] \[ = \bar{x}_1 + (\bar{x}_2 + \bar{x}_3) \bar{x}_4 \] **Explanation:** This step converts the function into a form suitable for CMOS implementation, focusing on the pull-down (NMOS) network. --- ### **Step 2: Draw CMOS Network and Assign W/L Ratios** #### **NMOS Pull-Down Network (Implements \( \bar{f} \)):** - **Parallel**: \( \bar{x}_1 \) OR the result of AND between (\( \bar{x}_2 + \bar{x}_3 \)) and \( \bar{x}_4 \). - The network is: - One branch: NMOS controlled by \( \bar{x}_1 \). - Second branch: Series connection of NMOS for \( \bar{x}_4 \) and a parallel connection of NMOS for \( \bar{x}_2 \) and \( \bar{x}_3 \). #### **PMOS Pull-Up Network:** - Complementary to NMOS: - Series for each parallel in NMOS, parallel for each series. - So, for the PMOS: - **Series**: PMOS for \( x_1 \). - **Parallel**: PMOS for \( x_2 \) and \( x_3 \) in series, and PMOS for \( x_4 \) in parallel to this series. #### **Width-to-Length Ratios:** - **Given:** \( W_p : W_n = 2:1 \) - For each PMOS, \( W/L = 2 \). - For each NMOS, \( W/L = 1 \). **Explanation:** This step maps the logic to CMOS transistor networks and assigns the appropriate W/L ratios based on the given constraint. --- ## **Final Answer** 1. **Logic implementation:** - Pull-down (NMOS) network implements \( \bar{f} = \bar{x}_1 + (\bar{x}_2 + \bar{x}_3)\bar{x}_4 \). - Pull-up (PMOS) network is the dual (series/parallel swapped). 2. **Transistor W/L ratios:** - **NMOS:** \( W/L = 1 \) - **PMOS:** \( W/L = 2 \) **This CMOS circuit correctly implements the function \( f = x_1 (x_2 x_3 + x_4) \) with the specified transistor sizing.**